`include "C:\Users\lenovo\Desktop\Files\Linear_RISCV\LR_ver_0\src\include\include.vh"
module 	ifu(
    input	    			clk,
    input	    			rst_n,
    input	    			ena,
    input	    [63:0]		pc_flush_i,
    input	        		branch_taken_i,
    output	    [31:0]		instr_if_o,
    output	    [63:0]		pc_if_o
);
    //PC_register
    reg     [63:0]      pc_next,pc_present;
    wire    [64:0]      pc_incre;
    assign pc_incre = pc_present+64'd4;
        //PC_next
        always@(*) begin
            if(!rst_n)begin
                pc_next=64'b0;
            end
            else begin
                pc_next=branch_taken_i?pc_flush_i:pc_incre[63:0];
            end
        end
        //pc_present
        always@(posedge clk or negedge rst_n)  begin
            if(!rst_n)begin
                pc_present<=64'd0;
            end
            else begin
                if(ena) begin
                pc_present<=pc_next;
                end
                else begin
                pc_present<=pc_present;
                end
            end
        end
    //imem_read
    wire    [9:0]      imem_addr;
        //addr_gen
            assign imem_addr = pc_present[21:2];
        //imem_instance
        IMEM imem_block(
            clk,
            rst_n,
            ena,
            imem_addr,
            instr_if_o			
        );
        //pc_if_o
        assign pc_if_o = pc_present;
endmodule